Thermal putty or thermal pad, which is better? Myths about thermally conductive materials, thermal conductivity and temperatures

1 - Overview and Introduction 2 - The real Chain of thermal Resistances 3 - The Benefits of a cooling Backplate 4 - All what you need is a better Cooling!

The gain from putty on the top side and between PCB and backplate

In this context, good putty or a high-quality pad on the top side can only do as much as the heatsink behind it can accept. In the equivalent network, the path from the die to the top of the housing is dominated by ΨJT, i.e. by the internal resistance of the DrMOS package, and the path from the pad into the heatsink is dominated by the limited contact area and the weakly energized area. If the thermal conductivity of the putty is increased from 3 to 6 or even 11 W/mK, only the small proportion attributable to the TIM is reduced. On the underside, i.e. between the PCB and the backplate, the role of the putty is different.

Here it mainly serves to distribute the diffuse waste heat, which has already penetrated the PCB, over a large area in the backplate and thus reduce the temperature level of the entire VRM zone. However, the PCB remains the dominant resistance, especially the FR-4 and the limited number of thermal vias. A putty with high thermal conductivity helps to better couple the backside to the backplate, but the calculation of the serial resistors shows that even here you only gain in the range of a few Kelvin in the steady state. The main benefit lies in reducing the local material stress and slowing down the ageing of solder joints and components, rather than in spectacularly sinking hotspots.

I have now created the curve graphic for the case in which putty is used over a very large area both on the top side between the VRM and cooler and on the rear side between the PCB and backplate. The x-axis again shows the thermal conductivity of the putty from 2 to 12 W/mK, while the y-axis shows the junction temperature Tj. Five curves are shown for cooler temperatures of 30, 35, 40, 45 and 50 °C.

In the model, both TIM paths are dependent on the putty conductivity: 0.5 mm putty over approx. 25 mm² DrMOS surface at the top, 3 mm putty over approx. 400 mm² contact to the backplate at the bottom. The backplate itself is set at 40 °C, i.e. slightly warmer than ambient, but below the hottest cooler scenarios. The internal package resistances remain unchanged at ΨJT = 15 K/W and ΨJB = 2 K/W, the board path is shown at around 13.3 K/W for the FR-4.

As expected, the curves fall sharply in the low conductivity range and flatten out significantly towards the top. At 30 °C cooler, for example, Tjunction drops from around 90.8 °C at λ ≈ 2 W/mK to around 80.0 °C at 6 W/mK and only to around 77.2 °C at 12 W/mK. For 40 °C coolers, the corresponding points are around 95.0 °C, 84.6 °C and 81.9 °C, and for 50 °C coolers around 99.3 °C, 89.2 °C and 86.7 °C. It can be seen very clearly that the jump from poor to medium putty (2 → 6 W/mK) adds around 10 Kelvin in each case, while the step from 6 to 12 W/mK only shifts around 2 to 3 Kelvin.

The five curves are almost parallel, which shows that the cooler temperature is still reflected almost 1:1 in the junction temperature. The putty value shifts the entire system downwards by a certain margin, but the distances between the 30, 35, 40, 45 and 50 degree curves remain largely constant across the entire λ range. This is the bottom line: with putty that is well bonded on both sides, the VRM junction can be improved in the two-digit Kelvin range if you switch from “poor” to “solid”, but beyond around 6 W/mK, the gains only increase logarithmically, while the absolute cooler temperature remains the dominant control lever. So the fan (or the cooling water) has to do the job here.

Thermal pad vs. putty

I have now calculated another comparison and generated two further sets of curves: one for a putty used over a large area on the top and back and one for a precisely dimensioned pad that only covers the VRM chips directly or the area directly below the VRM, but not the spaces in between and the adjacent PCB surfaces. I have again set the cooler temperature to 40 °C as an example, and the x-axis shows the thermal conductivity from 2 to 12 W/mK, as usual.

The first graph shows the junction temperature Tj over λ. The solid curve stands for large-area putty, the dashed curve for the pad that exactly covers the DrMOS. At λ ≈ 2 W/mK, Tj with a large area is around 95 °C, whereas with a small pad it is around 123 °C. At λ ≈ 6 W/mK, Tj drops to around 84.6 °C over a large area, but only to around 94 °C with a tight pad, and at λ ≈ 12 W/mK we end up roughly at 82 °C versus 86.5 °C. The difference in surface area in the low conductivity range is therefore well over 20 Kelvin and even with very good putty still around 4 to 5 Kelvin, although both variants have the same W/mK value.

The second graph shows the temperature of the PCB hotspot on the back. Here too, the solid line is the large-area putty, the dashed line the narrow pad. At λ ≈ 2 W/mK, the large area results in a backside temperature of around 51 °C, whereas with a narrow cover it is around 81 °C. With λ ≈ 6 W/mK we are at around 43.4 °C compared to 53.2 °C and with 12 W/mK at around 41.6 °C compared to around 46.5 °C. The surface effect is even more pronounced here than with the junction, because the additional thermal resistance of the narrow pad practically “constricts” the already poor FR-4 path and thermally decouples the rear side from the backplate.

The two curves thus show very clearly that the pure thermal conductivity of the material is only half the truth. A 6 W/mK putty, which also integrates the gaps, conductor tracks and vias over a large area, produces a junction temperature of just under 85 °C in the model and a rear side of around 43 °C. The same material as a narrow strip directly under the VRM chip row, on the other hand, leaves a junction temperature of just under 94 °C and a rear temperature of over 53 °C. The “missing” area practically acts as an additional series resistor. The smaller the covered area, the less heat reaches the backplate and the more concentrated the hotspot remains in the PCB, regardless of how expensive and how conductive the material nominally is. Putty can be distributed, but this is rather difficult with (harder) pads.

Conclusion and summary

The analysis of the thermal resistance chain of a DrMOS component shows very clearly that the most important control variables must not be considered in isolation. The heat path always starts in the junction, passes through the internal package resistors ΨJT and ΨJB and then splits into two external paths: upwards towards the cooler and downwards towards the PCB and backplate. The internal package resistors and the FR-4 path dominate the overall process to such an extent that an improved TIM only has a noticeable effect if it is applied to a sufficiently large surface and its thermal conductivity is not nullified by geometric restrictions.

This is precisely where the strength of Thermal Putty lies. Thanks to its adaptability, a significantly larger contact surface can be created, both above the VRM below the cooler and on the rear between the PCB and backplate. The rear side in particular benefits from this because the FR-4 path is the determining resistance there and every additional piece of contact surface improves the effective thermal dissipation. The curves show that the use of large-area putties reduces the PCB temperatures in the hotspot area by 20 Kelvin and more in some cases and also noticeably reduces the junction temperature. The higher the thermal conductivity, the flatter the gains because the FR-4 path then limits the overall effect. The decisive factor is therefore not just the W/mK figure, but above all the surface area and the use of the backplate path.

In retrospect, it can be seen that the structure of the entire thermal resistance chain remains unchanged. The putty does not replace either ΨJT or ΨJB, nor does it reduce the resistance in the FR-4 material itself. It can only optimize those sections that are actually penetrated by it. For this reason, tight pads that only selectively cover the VRM chip or the rear only lead to lower temperature gains and leave heat accumulation in the PCB. Only when the area is large enough do broadband thermal bridges occur, which dissipate the energy more evenly into the cooler or backplate.

Thermal putty is an effective means of optimizing the thermal connection of VRM components, but only if it is used generously and connects both the top and bottom sides sensibly. Especially in combination with a backplate, this results in an additional dissipation path that relieves the PCB and protects surrounding components from excessive thermal stress. The effect is clearly visible and in some scenarios is more important for stability and service life than a particularly highly advertised W/mK rating.

At the same time, it should be noted that even the best putty cannot override basic physics. It cannot compensate for an inefficient or undersized cooler, poor airflow or a thermally unfavorable layout. Putty achieves its greatest effect not as a replacement, but as a supplement to a functioning cooling concept. Practical experience therefore shows that the priority should remain clear: first a good cooler and a functioning airflow, then a large-area and cleanly executed thermal connection, and only then the question of which putty or pad method makes sense.