Intel Nova Lake: Big cache strategy, but only for the unlocked

Intel is preparing a new generation of processors with Nova Lake, which is apparently intended to compete specifically against AMD’s successful 3D-V cache chips. However, as is so often the case, the devil is in the detail and the blessing of the new cache technology, known as “bLLC” (Big Last Level Cache), is apparently strictly limited: Only the “unlocked” models of the Nova Lake family are to benefit from this generously increased L3 cache. The whole thing seems less like a comprehensive performance promise and more like a targeted consolation for overclockers and enthusiasts.

According to leaks, the bLLC will offer 144 MB of additional L3 cache, a significant leap, especially in direct comparison to previous Intel CPUs, which were nowhere near this dimension. This is Intel’s response to AMD’s 3D-V cache initiative, which has caused a stir since the Ryzen 7 5800X3D, particularly in the gaming sector. The fact that Intel is now concentrating on a “conventional” path, without stacked SRAM structures, speaks for a cautious response, not a radical change of course, but rather a symbolic “We can also cache, but differently”. Interestingly, the bLLC will apparently only appear on CPUs with a certain core configuration. Models with 8 performance cores (P cores) and 16 efficiency cores (E cores), supplemented by 4 additional LP-E cores, are being discussed as carriers of this cache extension. According to leaks, some Core Ultra 5 models should have precisely this combination and therefore be among the chosen few. For higher-end models such as the Core Ultra 7 or Ultra 9, however, the future of the cache remains uncertain. Although these processors have significantly more cores (up to 52 in the top configuration), there are no indications to date that they will also receive the bLLC. If this is confirmed, it would be an almost absurd irony: more cores, but less cache.

It is easy to understand why Intel only reserves the bLLC for “unlocked” SKUs: These CPUs are aimed at a solvent niche where every extra percentage point of performance counts and for which people are willing to dig deeper into their pockets. At the same time, however, it is also an admission that the broad market cannot or will not be served with comparable technology for the time being. It almost seems like a diplomatic capitulation to AMD’s technological lead in terms of cache design, disguised as strategic selection. But there should be no illusions: More cache does not automatically mean more performance. A large L3 cache can help, especially in scenarios with repeated data access, such as in many modern games. But if memory accesses are unpredictable or the application hardly benefits from the cache, the effect remains marginal. It therefore depends heavily on the overall architecture, the memory connection and the workload whether the bLLC brings a real advantage or just fills a nice data sheet.

The targeted performance gains of over 10 % in single-threading and up to 60 % in multi-threading should also be treated with caution. Without finally tested chips, these remain speculative values. And although some leaks suggest a Nova Lake CPU with 180 MB total memory thanks to double bLLC tiles, there has been no concrete confirmation from Intel itself so far. The bottom line is that bLLC presents itself less as a genuine technological innovation and more as a targeted marketing upgrade for a specific target group. Whilst AMD is spreading its cache offensive across almost the entire Ryzen lineup, Intel is sticking to a cautious single placement: a cannon for the enthusiast market, but not the big counterattack.

The real showdown is still to come anyway: AMD will counter with Zen 6 and advanced 3D-V cache technology, while Intel hopes to keep up with conventional methods. Whether this is enough will not be decided on paper, but in the benchmarks. Until then, bLLC remains a double-edged sword: impressive in theory, but with an uncertain effect in practice.

Source: Wccftech