ASRock X870E Taichi OCF Review and complete Teardown: Focus on the Essentials or more with less is almost impossible

1 - Introduction, unboxing and technical data 2 - Topology of voltage regulators and their cooling 3 - Teardown: USB 4 sub system, PC audio and WiFi 7 4 - Teardown: Chipset topology and other components 5 - Backplate, cooler, pads, and thermal conductivity 6 - UEFI, overclocking and own experience 7 - Performance and conclusion

The chipset area

The next step is to look at the central logic area of the board, which in the ASRock X870E Taichi OCF deliberately relies on two physically separate but functionally closely coupled chipsets. Even the assembly makes it clear that ASRock is not pursuing the minimal reference design here, but is consistently using the division specified by the X870E to achieve additional I/O resources, lane flexibility and clean separation of the functional domains.

The two chipsets themselves are designed as independent BGA packages, each with its own clearly defined peripherals. The first chip functions as a primary I/O hub with a direct connection to the CPU, i.e. it takes on classic tasks such as PCIe distribution, SATA connection and parts of the USB topology. The second chip works as an expansion hub, providing additional PCIe lanes, further USB controllers and internal interfaces. The separation reduces internal conflicts when using many high-speed interfaces at the same time and simplifies power and clock management, which is particularly advantageous under overclocking conditions. Another striking feature is the clean supply of both chips via dedicated switching regulator stages with clearly defined inductances and local decoupling, which indicates a deliberate minimization of interference coupling.

Two Nuvoton ICs, which play a central role in the overall platform management, are located in the immediate vicinity of these two chipsets. These are not simple auxiliary components, but fully-fledged embedded controllers or super I/O derivatives. These Nuvoton controllers are responsible for telemetry, voltage and temperature monitoring, fan control, status logic and the implementation of numerous board-specific functions, such as power sequences, debug logic, retry and safe boot functions or the control of onboard buttons and LEDs. The fact that ASRock uses two of these controllers here is not an end in itself, but follows a functional division. One controller is primarily responsible for the classic super I/O environment and power management, while the second takes on extended monitoring and OC-specific tasks. This separation reduces the load on the individual ICs, shortens response times and increases robustness, particularly in the event of extreme load changes or unstable operating states, as can occur during overclocking.

The placement of the Nuvoton ICs close to the relevant signal sources is no coincidence. Short sense lines, direct connection to voltage rails and close coupling to the clock and reset signals minimize measurement errors and latencies. This proximity is particularly important for precise telemetry, which is necessary for finely graduated voltage adjustments or the reliable interception of limit states. In practice, this means that the values recorded by the BIOS and the firmware are not only fast, but also reproducible and comparatively low-noise.

This area is supplemented by the ASMedia chip, which acts as a specialized I/O controller. In this case, it takes on the task of providing additional high-speed USB functions that cannot be covered directly by the CPU or completely by the chipset. ASMedia controllers are known for their ability to flexibly convert PCIe lanes into multiple USB ports, including protocol handling, retiming and, in some cases, signal processing. The surrounding passive components, especially the closely grouped capacitors and resistor networks, indicate differential high-speed pairs where impedance control and clean supply are critical. Again, it is clear that ASRock does not consider the controller in isolation, but integrates it into a cleanly defined block, with clear current paths and sufficient decoupling from the neighboring chipset domains.

The result is a very deliberately designed platform architecture. The dual chipset solution is not only implemented formally, but also utilized functionally. The two Nuvoton controllers ensure a finely tuned interplay of monitoring, control and security, while the ASMedia chip is used specifically where specialized I/O functionality is required. ASRock’s advertising claims about stability, control and overclocking suitability have a comprehensible technical basis here, as the implementation shows a clear separation of functional areas, short signal paths and a redundancy of control and monitoring logic that goes far beyond what is usual with simpler motherboards.

Other areas

In the last section, I will now simply proceed picture by picture and assign the recognizable components to a clearly defined functional group. I refer to the markings legible on the chips, to typical reference designs of the manufacturers and to the usual topology of current AM5 mainboards from ASRock. The first picture shows the area around the power supply of the additional logic, specifically several small step-down converters with coil markings such as “1R0” and “2R2”. These buck regulators supply typical auxiliary consumers such as USB controllers, network PHYs, audio subsystems and controller MCUs with 5 V, 3.3 V or lower logic voltages. The topology is classic, synchronous buck regulators with integrated MOSFETs, flanked by ceramic capacitors for smoothing and small shunts or sense resistors for current monitoring. The Nuvoton component in the immediate vicinity, marked Nuvoton NCTxxxx in this picture, acts as an embedded controller or hardware monitor. It records voltages, temperatures and fan speeds and also performs board management tasks such as power sequencing and ACPI signaling. This role is typical for ASRock designs and is in line with the advertised “Smart Fan” and monitoring functions.

The second image shows a group of Phison components, specifically several identical ICs in a symmetrical arrangement. These are not SSD controllers, but Phison re-drivers or retimer or switch components for high-speed signals, usually PCIe or USB4. In this constellation, it can be assumed that they are used for signal processing of the M.2 slots or a PCIe bifurcation path. Phison is a typical supplier for PCIe signal conditioning, especially for long tracks or multiple slots. The function group is therefore clearly assigned to high-speed signal integrity, a point that ASRock often advertises with phrases such as “server-grade PCB” or “PCIe signal conditioning”. The actual assembly shows that these statements are at least technically substantiated.

The third image shows a single component marked MXIC MX25V4035F. This is clearly an SPI-NOR flash from Macronix. This chip is used as non-volatile memory for firmware, either for additional controllers or for functions such as BIOS flashback. The close proximity to labels such as “FLASH” or “BIOS” and to a small logic IC confirms this assignment. The capacity of 4 Mbit is sufficient for dedicated controller firmware or for a separate boot block, but not for a complete UEFI, which is usually located on a larger SPI flash. ASRock likes to use such additional flash devices for redundancy or for independent flashback functions without an installed CPU.

The fourth picture shows a larger Nuvoton controller, here with clear ARM labeling. This module takes on an extended management role, often as a baseboard management controller in the broader sense, even if it is not a fully-fledged BMC as in servers. It controls RGB logic, monitors sensors, manages firmware updates and communicates with the main BIOS. In the topology, it functions as an independent intelligence layer alongside the actual UEFI system. On the marketing side, this is often abstracted as “ASRock Super IO” or “Polychrome Engine”, but technically this is exactly the microcontroller behind it.

The fifth image shows a component labeled AS393M. This is a specialized controller that is typically used as a power controller or protection IC, for example for overvoltage, ESD protection or power path management. The surrounding resistor networks and ceramic capacitors indicate an analog function, not pure digital logic. This group of functions is part of the board’s electrical protection, an aspect that ASRock likes to market under buzzwords such as “Full Spike Protection”. The real implementation shows at least the usual protection mechanisms, but without exotic additional circuits.

The next image shows an area labeled “Flashback 3”, including small logic ICs and passive components. This is where the dedicated BIOS flashback circuit is implemented, which allows the UEFI to be updated without CPU or RAM. The aforementioned Macronix flash plays a role here, as does a small microcontroller or logic component that controls the flash process. Topologically, this is a clearly separated sub-circuit, electrically decoupled from the rest of the system, which increases the robustness of this function.

The following picture shows the GL9950. This is a USB hub controller from Genesys Logic. The GL9950 is a USB 3.x hub that distributes an upstream port to several downstream ports. In ASRock boards, this chip is often used to provide internal headers, front panel ports or additional rear USB ports. The function group is clearly assigned to the USB extension. Marketing statements such as “plenty of USB ports” are based precisely on such additional controllers, as the native ports of the AMD chipset alone are not sufficient.

The following picture shows an ITE controller with a typical QFP housing shape. ITE is known for super I/O components and additional controllers for legacy functions, GPIO expanders and sometimes also for USB bridge tasks. In this context, the ITE chip is very likely to take on tasks relating to internal headers, sensors or debug interfaces. The trace routing shows numerous slow signals, which speaks against high-speed I/O and in favor of classic board peripherals.

The next image shows a NUC121Z02, an ARM-based microcontroller from Nuvoton. This is often used for dedicated control tasks, such as BIOS flashback, RGB controllers or special diagnostic functions. Its position close to buttons, LEDs or debug pads confirms this role. Topologically, it is an autonomous node in the system that can operate independently of the main SoC.

The Realtek RTL8126 can be seen in the last image. This is a 5 GbE PHY. This PHY is connected via a serial interface to the actual MAC, which is located either in the chipset or in a separate network controller. The RTL8126 handles the physical Ethernet layer, including autonegotiation, line encoding and energy-saving functions. The surrounding magnetics are outsourced and sit closer to the RJ45 socket. The function group is thus clearly assigned to the network subsystem. ASRock often advertises this area with “Dragon LAN” or similar terms, but technically it is an established Realtek standard PHY without exotic special functions.

After evaluating all the details assessed so far, this picture-by-picture analysis also shows a very classic, but quite elaborately equipped motherboard design. The topology follows clearly separated function groups for power supply, management, USB expansion, network and firmware handling. ASRock’s marketing claims are largely supported by real additional controllers and clean segmentation, even if behind the well-sounding terms there are usually well-known standard ICs with clearly defined tasks.