Deceptive packaging, bottom of the barrel or stroke of genius? – Patriot Viper Venom DDR5-6400 CL32 2x 16 GB kit with SK Hynix 8 Gbit “H-Die” ICs in test with teardown and overclocking

1 - Unboxing and specifications 2 - SPD information and special properties of the ICs 3 - Heatsink test with external K-type sensor 4 - Teardown and PCB analysis 5 - Compatibility and overclocking 6 - Benchmarks – Synthetics 7 - Benchmarks – Gaming 8 - Summary and conclusion

SPD information and special properties of the ICs

In the SPD we find all the important information about the RAM modules that the CPU and mainboard also need for stable joint operation. It is important to understand that the SPD is only an EEPROM memory chip and the information it contains is only as good as the manufacturer has programmed it to be.

First of all, the capacity of the modules is stored here, together with the nominal clock rate of 3200 MHz (DDR5-6400) and the manufacturer Patriot Memory (PDP Systems). The product number is only referred to as 6400 Series, the exact part number is missing. At least the serial number and production week are given, but this should only serve as a hint for end customers to identify the modules beyond doubt via software.

Now we come to the really exciting part: The ICs are listed as manufacturer SK Hynix, Stepping H-Die (4.8) and Density 8192 Mb. In summary, SK Hynix 8 Gbit H-Die. But caution is advised here, as Patriot itself has stored this information and according to the public documents from SK Hynix there is no 8 Gbit H-Die. Is it an internal designation or has Patriot simply used some letter? This question remains unanswered.

But how is it possible that these ICs appear in 2025 at all, when 16 Gbit was the entry-level capacity at the beginning of the DDR5 era a few years ago? This can be explained by the following detail: Number of Bank Groups 8 is standard for DDR5 x8 ICs, but Banks per Group 2 is unusual – normally there are 4.

It is therefore obvious that these are rejects, i.e. ICs in which not all banks function correctly for all bank groups. During the first tests after production, these are then rejected immediately. However, instead of disposing of them, the defective memory cell units are deactivated and the ICs are recycled as 8 Gbit capacity. This is also familiar from CPUs: if cores or cache areas do not function or clock correctly after the production of a top-end CPU, these areas are deactivated. An i9 becomes an i7, a Ryzen 9 becomes a Ryzen 7 (to put it simply).

So these 8 Gbit H-die ICs are probably actually 16 Gbit A-die ICs that had some kind of production defect. Accordingly, the clock and timing characteristics are likely to be very similar, but with half the capacity. In order to still be able to offer a 16 GB module or 32 GB kit, ICs are simply installed in 2 ranks per module on both sides by Patriot. You could say that we actually have 2 classic 32 GB dual-rank DDR5 modules here, where half of the banks within the bank groups have been deactivated.

Now the question naturally arises whether halving the banks per bank group has an impact on performance. Practically speaking, the bank groups are the “work units” that are addressed by the RAM controller of the CPU with the activate timings. That was also a big argument from DDR5 to DDR4, that the bank groups were doubled from 4 to 8 and thus better multitasking was made possible, so to speak. However, if the banks per bank group are halved again, the same amount of work has to be distributed across more bank groups. Each time a bank group is addressed, it must first be activated. Now it depends on the respective IC how quickly a bank group can be activated on the one hand, and on the other hand how quickly the operations within the bank group are handled by the banks. Expressed in timings: tRRD(_s/_l) against tCCD(_s/_l)

Of course, it also depends on the IMC of the CPU and to what extent it can handle the atypically few banks per bank group or how well it has been optimized for this. In theory, there are therefore too many variables to be able to derive the performance impact of our ICs’ special feature beyond doubt. But fortunately there is reality and benchmarks.

The other ICs on the board are supposedly both from IDT (Renesas). The PMIC is of type PMIC5100 and supports VDD/VDDQ values > 1.435 V. The SPD is a type SPD5118, which also integrates the temperature sensor of the modules.

Finally, the XMP profiles should of course be mentioned. Patriot supplies 3 of these:

• Profile 1: DDR5-6400, tCL 32, tRCD 40, tRP 40, tRAS 84, tRC 117, tRFC 940, tRFC2 510, tRFCsb 415, tWR 96 at 1.4 V VDD/VDDQ
• Profile 2: DDR5-6200, tCL 40, tRCD 40, tRP 40, tRAS 76, tRC 117, tRFC 916, tRFC2 496, tRFCsb 403, tWR 94 at 1.35 V VDD/VDDQ
• Profile 3: DDR5-6000, tCL 30, tRCD 40, tRP 40, tRAS 76, tRC 117, tRFC 884, tRFC2 480, tRFCsb 390, tWR 90 at 1.35 V VDD/VDDQ

Patriot is therefore fully exploiting the memory limits of the DDR5 SPD for Intel XMP 3.0, although the profiles are quite similar. Intel CPUs actually benefit from significantly higher clock rates, which is why such low XMP profiles are unusual, but we are also looking at a dual-rank kit here. Since more ranks are known to have a negative effect on the clock potential, 6400 Mbps at the maximum is quite reasonable.

The profiles are also very well suited to AM5 CPUs, as these fully utilize the 1:1 mode in this area. As always, you just have to make sure that the UCLK DIV1 MODE is manually set to UCLK = MEMCLK for profiles above 6000 Mbps in order to prevent the auto value UCLK = MEMCLK / 2 and the associated loss of performance.